1. Field of the Invention
The present invention relates to a semiconductor device having a circuit comprising thin-film transistors on a substrate with an insulating surface and to a method of manufacture thereof. More specifically, the invention relates to a constitution of an electrooptical device represented by a liquid crystal display and of an electronic apparatus mounting the electrooptical device. In this specification, the semiconductor device generally denotes devices that function by utilizing semiconductor characteristics and includes the electrooptical devices and the electronic apparatus mounting the electrooptical devices.
2. Related Art
The thin-film transistor (hereinafter abbreviated to TFT) can be fabricated on a transparent glass substrate and therefore has been actively applied to active matrix liquid crystal displays. Because the TFT formed of a semiconductor layer having a crystal constitution (hereinafter referred to as a crystalline TFT) has a high mobility, high resolution image display can be realized by integrating functional circuits on the same substrate.
In this specification, the semiconductor film having the crystal constitution includes a single crystal semiconductor, a polycrystalline semiconductor, and a microcrystal semiconductor. It also includes semiconductors disclosed in official gazettes JP-A 7-130652, JP-A 8-78329, JP-A 10-135468, and JP-A 10-135469.
To construct an active matrix liquid crystal display, the pixel area alone requires 1 to 2 million crystalline TFTs and, when peripheral functional circuits are constitution, additional numbers of crystalline TFTs are necessary. To operate the liquid crystal display stably requires securing reliability of individual crystalline TFTs.
The characteristic of a field-effect transistor such as TFT can be constitution as comprising a linear region where a drain current increases in proportion to a drain voltage, a saturation region where the drain current saturates even if the drain voltage increases, and a cut-off region where the current ideally does not flow even when the drain voltage is applied. In this specification, the linear region and the saturation region are called ON regions of TFT and the cut-off region is called an OFF region. The drain current in the ON region is called an ON current and the current in the OFF region an OFF current.
The pixel area of the active matrix liquid crystal display comprises n-channel TFTs (hereinafter referred to as pixel TFTs) and, because a gate voltage with an amplitude of about 15-20 V is applied thereto, needs to satisfy both of the characteristics of the ON region and the OFF region. On the other hand, the peripheral circuits for driving the pixel area basically comprise CMOS circuits and their characteristics of the ON regions are mainly important. The crystalline TFTs, however, have a problem that the OFF current easily increases. Further, a degradation phenomenon has often been observed when driving the crystalline TFT for an extended period of time results in the mobility and ON current decrease and the OFF current increases. One of the possible causes is presumed to be a hot carrier injection phenomenon caused by a high electric field near the drain.
In the field of the MOS transistor, a lightly doped drain (LDD) constitution has been known as a method for reducing the OFF current and alleviating the high electric field near the drain. This constitution has a low concentration impurity region on the inner side of the source and drain regions, i.e., on the side of the channel forming region. This low concentration impurity region is called an LDD region.
The LDD constitution is also known to be formed similarly in the crystalline TFT. For example, with the gate electrode as a mask, a first impurity injection process forms a low concentration impurity region that will form an LDD region, and then sidewalls are formed on both sides of the gate electrode by using an anisotropic etching technique. With the gate electrode and the sidewalls as a mask, a second impurity injection process forms a high concentration impurity region that will form a source region and a drain region.
Although the LDD constitution can render the OFF current lower as compared with that of the ordinary constitution TFT, the LDD constitution has a drawback that because a series resistance component increases for the constitution reason, the TFT ON current, too, is reduced. Further, the deterioration of the ON current cannot be prevented completely. To compensate for this drawback a constitution has been known to be used in which the LDD region overlaps the gate electrode with the gate insulating film interposed therebetween. There are several methods for making this constitution, such as GOLD (Gate-drain Overlapped LDD) and LATID (Large-tilt-angle implanted drain). In this overlapping constitution the high electric field near the drain can be alleviated to increase the tolerance for hot carriers and at the same time prevent reduction in the ON current.
It is also confirmed that in the crystalline TFT, too, the provision of the LDD constitution increases withstandability against hot carriers as compared with that of the simple constitution TFT having only the source region, drain region and channel forming region, and that the use of the GOLD constitution produces an excellent effect. This fact is described in xe2x80x9cA Novel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performance,xe2x80x9d by Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97-523.
In the crystalline TFT, forming the LDD constitution has proved to be an effective means for suppressing the hot carrier injection phenomenon. Further, the use of the GOLD constitution is found to be able to prevent a reduction in the ON current, which was observed in the LDD constitution, and also to produce a preferable result in terms of reliability.
Although the GOLD constitution can prevent degradation of the ON current, it has a drawback that when a high gate voltage is applied thereto at the OFF characteristic, the OFF current is increased, as observed in the pixel TFT in particular. An increase in the OFF current in the pixel TFT produces undesired effects such as increased power consumption and abnormal image display. This is constitution due to an inverted layer which, because of the characteristic of the OFF region, is formed in the LDD region overlapping the gate electrode.
As described above, to realize a high level of reliability in the crystalline TFT requires a comprehensive study on the constitution of the device. For this reason, it has been desired that the GOLD constitution be formed. With the conventional method, however, although the LDD region can be formed self-aligningly, the process of forming the sidewall film by an anisotropic etching is not suited for processing a large-area glass substrate like the one used in the liquid crystal display. Further, because the length of the LDD region is determined by the width of the sidewall, the degree of freedom in designing device dimensions is severely restricted.
If, as in the pixel TFT, the characteristics of both the ON region and the OFF region are important and an attempt is made to meet the required level of their reliability and prevent an increase in the OFF current, the conventional GOLD constitution is not sufficient.
A first object of the invention is to provide a crystalline TFT having a constitution in which a gate electrode and an LDD region are overlapped by a simpler method than conventional ones, and to provide a method of manufacturing such a crystalline TFT. The GOLD constitution has a problem that when a high gate voltage is applied thereto at the OFF characteristic, the OFF current is increased. It is therefore a second object of the invention to provide a constitution capable of preventing an increase in the OFF current and a method of manufacturing such a constitution.
For a pixel area of the liquid crystal display and drive circuits made basically of CMOS circuits arranged around the pixel area, it is a third object of the invention to provide a constitution in which the LDD region of at least an n-channel TFT overlaps a gate electrode and which can prevent an increase in the OFF current, and to provide a method of manufacturing the constitution.
FIG. 17 schematically shows the constitution of a TFT and its Vg-Id (gate voltage-drain current) characteristic, based on the findings obtained so far. FIG. 17(A-1) shows the simplest constitution of TFT in which the semiconductor layer comprises a channel forming region, a source region and a drain region. In the characteristic shown in FIG. 17(B-1), +Vg side represent the ON region of TFT and xe2x88x92Vg side an OFF region. A solid line represents an initial characteristic and a dashed line a characteristic after application of a bias stress. In this constitution, the ON current and the OFF current are both high and the degradation due to the bias stress is large, so that this constitution cannot be applied to the pixel TFT.
FIG. 17(A-2) shows a constitution in which a low concentration impurity region that will make an LDD region is added to the (A-1) constitution in such a way that the gate electrode does not overlap the LDD region. In this constitution, although it is possible to suppress the OFF current to some extent, the degradation of the ON current cannot be prevented, as shown in (B-2). FIG. 17(A-3) shows a constitution, also called a GOLD constitution, in which the LDD region completely overlaps the gate electrode. As shown in (B-3), the degradation of the ON current can be suppressed but there is a problem that the OFF current is higher than that of the (A-2) LDD constitution.
Hence, the constitution shown in FIGS. 17(A-1), (A-2), and (A-3) cannot simultaneously satisfy both of the ON region characteristic and the OFF region characteristic required by the pixel area, within the reliability requirement. It has been found, however, that the use of the constitution of FIG. 17(A-4) can prevent deterioration of the ON current and suppress an increase in the OFF current. This can be achieved by dividing the LDD region into a region that overlaps the gate electrode and a region that does not. The LDD region overlapping the gate electrode has a function of suppressing a hot carrier injection phenomenon and the LDD region not overlapping the gate electrode has a function of preventing an increase in the OFF current.
In the present invention, a gate electrode is formed of a plurality of layers in order to obtain a constitution in which the LDD region overlaps the gate electrode, by a step of forming a first conductive layer of the gate electrode and a step of forming a second conductive layer of the gate electrode. After the first conductive layer forming step, the invention performs a step of first impurity element doping to form a first impurity region that will make the LDD region and, after the second conductive layer forming step, performs a step of a second impurity element doping to form a second impurity region that will make a source region and a drain region. Then, a part of the second conductive layer is removed to form a TFT which has a region where the LDD region does not overlap the second conductive layer.
Therefore, the constitution of this invention disclosed in this specification is characterized in that, in a semiconductor device having a pixel area where an n-channel thin-film transistor is provided in each pixel, the gate electrode of the n-channel thin-film transistor has a first conductive layer formed in contact with a gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film; and that the semiconductor layer of the n-channel thin-film transistor has a channel forming region, a first impurity region of one conductivity type formed in contact with the channel forming region, and a second impurity region of one conductivity type formed in contact with the first impurity region, the first impurity region having a part thereof overlapping a region of the second conductive layer that is in contact with the gate insulating film.
Another constitution of this invention is characterized in that, in a semiconductor device including a CMOS circuit having an n-channel thin-film transistor and a p-channel thin-film transistor, the gate electrode of the n-channel thin-film transistor has a first conductive layer formed in contact with a gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film; and that the semiconductor layer of the n-channel thin-film transistor has a channel forming region, a first impurity region of one conductivity type formed in contact with the channel forming region, and a second impurity region of one conductivity type formed in contact with the first impurity region, the first impurity region having a part thereof overlapping a region of the second conductive layer that is in contact with the gate insulating film.
Still another constitution of this invention is characterized in that, in a semiconductor device which includes a pixel area where an n-channel thin-film transistor is provided in each pixel and a CMOS circuit having an n-channel thin-film transistor and a p-channel thin-film transistor, the gate electrode of the n-channel thin-film transistor has a first conductive layer formed in contact with a gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film; and that the semiconductor layer of the n-channel thin-film transistor has a channel forming region, a first impurity region of one conductivity type formed in contact with the channel forming region, and a second impurity region of one conductivity type formed in contact with the first impurity region, the first impurity region having a part thereof overlapping a region of the second conductive layer that is in contact with the gate insulating film.
In the constitution of this invention described above, the first impurity region forms the LDD region and the second impurity region forms the source region or drain region. The gate electrode of the p-channel thin-film transistor comprises a first conductive layer formed in contact with a gate insulating film and a second conductive layer formed in contact with the first conductive layer and the gate insulating film. The semiconductor layer of the p-channel thin-film transistor comprises a channel forming region and a third impurity region of a conductivity type reverse to one conductivity type formed in contact with the channel forming region.
The constitution of this invention described above may comprise a semiconductor layer and a storage capacitance, wherein the semiconductor is provided in contact with the second impurity region and has the same conductivity type as the first impurity region, and wherein the storage capacitance is provided by a capacitive line formed by the gate insulating film, the first conductive layer and the second conductive layer.
In the constitution of this invention, the first conductive layer is formed of one of elements selected from titanium (Ti), tantalum (Ta), Tungsten (W) and Molybdenum (Mo), or an alloy made mainly of these elements.
The first conductive layer comprises a conductive layer (A) formed in contact with the gate insulating film and one or more conductive layers formed over the conductive layer (A). It is preferred that the conductive layer (A) formed in contact with the gate insulating film be formed of one element selected from titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo), or formed of an alloy made mainly of these elements, and that at least one of the one or more conductive layers formed over the conductive layer (A) be formed of one element selected from aluminum (Al) and copper (Cu) or formed of an alloy made mainly of these elements. The second conductive layer should preferably be formed of one element selected from titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo), or formed of an alloy made mainly of these elements.
To realize the constitution described above, the method of manufacturing a semiconductor device according to the invention comprises: a first step of forming a semiconductor layer over a substrate having an insulating surface; a second step of forming a gate insulating film in contact with the semiconductor layer; a third step of forming a first conductive layer in contact with the gate insulating film; a fourth step of forming a first impurity region by adding an element belonging to Group 15 in the periodic table to the semiconductor layer with the first conductive layer as a mask; a fifth step of forming a second conductive layer in contact with the first conductive layer and the gate insulating film; a sixth step of forming a second impurity region by adding an element belonging to Group 15 in the periodic table to the semiconductor layer with the second conductive layer as a mask; and a seventh step of removing a part of the second conductive layer.
Another manufacturing method of the invention comprises: a first step of forming a first semiconductor layer and a second semiconductor layer over a substrate having an insulating surface; a second step of forming a gate insulating film in contact with the first semiconductor layer and the second semiconductor layer; a third step of forming a first conductive layer in contact with the gate insulating film; a fourth step of forming a first impurity region by adding an element belonging to Group 15 in the periodic table to at least the first semiconductor layer with the first conductive layer as a mask; a fifth step of forming a second conductive layer in contact with the first conductive layer and the gate insulating film; a sixth step of forming a second impurity region by adding an element belonging to Group 15 in the periodic table to at least the first semiconductor layer with the second conductive layer as a mask; and a seventh step of forming a third impurity region by adding an element belonging to Group 13 in the periodic table to only the second semiconductor layer with the second conductive layer as a mask.
Still another manufacturing method of the invention comprises: a first step of forming a first semiconductor layer and a second semiconductor layer over a substrate having an insulating surface; a second step of forming a gate insulating film in contact with the first semiconductor layer and the second semiconductor layer; a third step of forming a first conductive layer in contact with the gate insulating film; a fourth step of forming a first impurity region by adding an element belonging to Group 15 in the periodic table to at least the first semiconductor layer with the first conductive layer as a mask; a fifth step of forming a second conductive layer in contact with the first conductive layer and the gate insulating film; a sixth step of forming a second impurity region by adding an element belonging to Group 15 in the periodic table to at least the first semiconductor layer with the second conductive layer as a mask; a seventh step of removing a part of the second conductive layer; and an eighth step of forming a third impurity region by adding an element belonging to Group 13 in the periodic table to only the second semiconductor layer with the second conductive layer as a mask.
The manufacturing method of the invention described above is characterized in that the first impurity region forms the LDD region and the second impurity region forms a source region and a drain region. The manufacturing method further includes: a step of adding an element belonging to Group 15 in the periodic table in the same concentration as in the first impurity region to a semiconductor layer extending from the second impurity region; and a step of forming a capacitive line by the first conductive layer and the second conductive layer.
In the constitution of this invention, the first conductive layer is formed of one element selected from titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo), or formed of an alloy made mainly of these elements.
The invention is further characterized in that the first conductive layer comprises a conductive layer (A) formed in contact with the gate insulating film and one or more conductive layers formed over the conductive layer (A); that the conductive layer (A) is formed of one element chosen from titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo), or formed of an alloy made mainly of these elements; that at least one of the conductive layers formed over the conductive layer (A) is formed of one element chosen from aluminum (Al) and copper (Cu) or formed of an alloy made mainly of these elements; and that the second conductive layer is formed of one element selected from titanium (Ti), tantalum (Ta), tungsten (W) and molybdenum (Mo), or formed of an alloy made mainly of these elements.